module non_blocking(Clk_50M, Ina, Outb, Outc);

	input Clk_50M;
	input Ina;
	output reg Outb;
	output reg Outc;
	
	always @(posedge Clk_50M) begin
		Outb <= Ina;
		Outc <= Outb;
	end

endmodule
